Photolithography is a vital step in the fabrication of highly-integrated semiconductor devices having a stacked structure. The photolithography process may be performed a number of times during the fabrication of semiconductor devices. During each photolithography step, it is required that a corresponding photomask in each process be aligned precisely with the target semiconductor substrate in order to minimize misalignment between discrete layers. To facilitate the operation, alignment of the photomask and the semiconductor substrate is necessary before performing the photolithography process. An alignment key is provided on a predetermined portion of the semiconductor substrate in order to perform the alignment operation. The alignment key is commonly formed on a scribe lane region between chip dyes in accordance with the fabrication processes. One exemplary approach for forming such an alignment key is disclosed in U.S. Pat. No. 5,475,268.
In the fabrication of a highly-integrated DRAM device, when the width of a bit line is reduced, the distance between storage node contact plugs formed on both sides of the bit line is also reduced. Therefore, when storage node electrodes contacting the storage node contact plugs are formed, it is required that the storage node electrodes be aligned precisely along the width direction of the bit line. In the case that the storage node electrodes are misaligned along the width direction of the bit line, an electrical bridge may occur between the storage node contact plugs provided on both sides of the bit line due to the storage node electrodes. In order to prevent the misalignment of the storage node electrodes, an alignment key (hereinafter, referred to as “bit line key”) can be used that is concurrently formed with the bit line during the formation of the bit line, after forming the alignment key on the top of the scribe lane region. More specifically, a molding insulating layer is formed on a resultant structure including the bit line and the storage node electrodes, which are sequentially formed. Then, the molding insulating layer is patterned, thereby forming storage node electrode holes in which the storage node electrodes will be formed. At this time, by aligning a photomask for patterning the insulating layer with the bit line key, misalignment of the storage node electrodes along the width direction of the bit line can be mitigated.
FIGS. 1 to 3 are sectional views illustrating a process of forming an alignment key during the fabrication of a conventional DRAM device. FIGS. 1 to 3 are sectional views illustrating a scribe lane region defined in a semiconductor substrate.
Referring to FIG. 1, a first interlayer insulating layer 3 is formed on a semiconductor substrate 1. The first interlayer insulating layer 3 is also formed in a cell region of the DRAM device (not shown) on which gate patterns are formed. Further, bit line contact pads and storage node contact pads are formed between the gate patterns. Then, a deposition process of forming a conductive layer and a patterning process to form a bit line are performed on the first interlayer insulating layer 3 of the cell region. During the processes, a bit line key pattern 5 is concurrently formed on the first interlayer insulating layer 3 of the scribe lane region.
Referring to FIG. 2, a second interlayer insulating layer 7 is formed to cover the bit line key pattern 5. In the case of using the bit line key pattern 5 as an alignment key to form a storage node electrode hole, the bit line key pattern 5 may be unrecognizable using merely an optical method using the alignment equipment in a stepper due to a molding insulating layer and a hard mask pattern subsequently formed on the second interlayer insulating layer 7 to form the storage node electrode holes. Particularly, the possibility of the misalignment may be further increased when the thickness of the molding insulating layer is increased with the high integration of the DRAM device, and when an amorphous carbon layer having a low light transmittance is used as the hard mask pattern. Therefore, the process of forming the alignment key having an appropriate step height difference is performed by etching the interlayer insulating layers on the scribe lane region together during an anisotropic etch process of forming the storage node contact holes in the cell region. That is, since the bit line key pattern 5 has a high etch selectivity with respect to the interlayer insulating layers 3, 7, an alignment key pattern 9 is formed as shown in FIG. 2. During the process, the first interlayer insulating layer 3 below the bit line key pattern 5 may be etched to expose the semiconductor substrate 1 since the first interlayer insulating layer 3 does not include an etch stop layer. In this case, the step height difference h1 formed by the alignment key pattern 9 may be excessively increased.
Referring to FIG. 3, after the alignment key pattern 9 is formed, a third interlayer insulating layer 11 is formed to cover the scribe lane region having the alignment key pattern 9 formed thereon. A capacitor is formed to have the storage node electrodes inside the third interlayer insulating layer 11 of the cell region. Since the third interlayer insulating layer 11 formed on the alignment key pattern 9 is affected by the step height difference h1 formed by the alignment key pattern 9, a top portion of the third interlayer insulating layer 11 has a global step height difference h2. Therefore, when the step height difference h1 formed by the alignment key pattern 9 becomes excessively large as shown in FIG. 2, the global step height difference h2 is also increased. In this case, because the global step height difference h2 has an influence on a main chip region adjacent to the scribe lane region, the flatness of the third interlayer insulating layer 11 formed on top of the main chip region may be deteriorated. As a result, the difference in height may adversely affect subsequent fabrication processes, for example pattern deterioration can occur during a photolithography process of forming a metal interconnection on the third interlayer insulating layer 11.